MIPI homepage CMOS prescaler basics
PDF) Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices
Schematic timing diagram of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Figure 1 from A 45 mW RTD/HBT MOBILE D-Flip Flop IC Operating up to 32 Gb/s | Semantic Scholar
PPT - Advantages of Using CMOS PowerPoint Presentation, free download - ID:3409185
A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider: Ravindran Mohanavelu and Payam Heydari | PDF
PDF) Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices
A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
KR100969864B1 - Cml type d flip-flop and frequency divide-by-odd number using the same - Google Patents
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
High speed CML latch using active inductor in 0.18μm CMOS technology | Semantic Scholar
Current-Mode-Logic (CML) Latch | EveryNano Counts
ECEN620: Network Theory Broadband Circuit Design Fall 2022
adding reset function to D Flip FLOP | Forum for Electronics
High Speed Digital Blocks
DFF-based CMOS clock divider. | Download Scientific Diagram
Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Figure 2 from New CML latch structure for high speed prescaler design | Semantic Scholar
Figure 16.23 from Direct-coupled Fet Logic (dcfl) @bullet Source-coupled Fet Logic (scfl) @bullet Advanced Mesfet/hemt Design Examples Iii-v Hbt for Circuit Designers @bullet Current-mode Logic @bullet Emitter-coupled Logic @bullet Ecl/cml Logic Examples @
Analysis and Design of High-Speed CMOS Frequency Dividers
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
Help me calculate the device size of CML/SCL latch design and simulate the gain of it | Forum for Electronics
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Asynchronous Primitives in CML - ppt download
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
